Special Reports

The Sub-2nm Paradox

By: Ed Sperling

Reducing variation in manufacturing, monitoring behavior over time, and targeting specific workloads can have a big impact on power, performance,...
Toward Agentic Verification

By: Brian Bailey

Using AI agents for verifying designs holds huge potential, but can it deliver? And what comes next?
Flash Getting Stacked High-Bandwidth Version

By: Bryon Moyer

Inspired by HBM, HBF could improve AI efficiency in 3D flash memory.

 more »

Top Stories

PCIe Benefits From AI, Despite Scaling Protocols

 CXL is also gaining traction in AI processing, while MIPI and others are growing at the...
June 10th, 2026 By Bryon Moyer

AI Models Transform Defect Inspection And Review, But Can Fail To Scale

 Majority of AI initiatives falter; synthetic data gaining traction due to limited real-...
June 9th, 2026 By Laura Peters

Why Analog And Mixed-Signal Chips Resist Adaptive Test

 Analog behavior is difficult to compress into simple pass/fail decisions that could red...
June 9th, 2026 By Gregory Haley

Co-Packaged Optics Testing Faces Steep Data Center Ramp

 Scaling to tens of millions of CPO units per year requires the industry to first settle...
June 9th, 2026 By Anne Meixner

Orbital Data Centers Are Souped-Up Satellites – For Now

 Satellite constellations with extra onboard compute are several steps away from handlin...
June 4th, 2026 By Liz Allan

Keeping Security Algorithms Current Is Getting Harder

 As threats evolve faster, protecting security algorithms from design through manufactur...
June 4th, 2026 By Ann Mutschler

AI-Defined Vehicles Increase Pressure On Auto Ethernet Reliability

 Time-sensitive networking and MACsec allow Auto Ethernet to handle safety-critical func...
June 4th, 2026 By Liz Allan

GaN Power Devices Power Up

 New research points to safer devices with less loss at low voltages, but problems remai...
June 3rd, 2026 By Katherine Derbyshire

Swapping Out Chiplets: I/Os Vs. Compute

 Multi-die assemblies give chip architects the option to change some dies while keeping ...
May 28th, 2026 By Liz Allan

Observability Is Essential For Modern Silicon

 What on-die visibility reveals, and why it's especially important for AI, automotive, a...
May 28th, 2026 By Ann Mutschler

Curvilinear Masks Push The Limits Of Inspection And Metrology

 As high-NA EUV approaches, mask makers need new metrics, model-based checks, and curvil...
May 27th, 2026 By Gregory Haley

With Chiplets, What Role Does Economics Play?

 Costs can rise with chiplets. Will that change? Will it matter?
May 21st, 2026 By Bryon Moyer

Low-Temp Solders Are Suddenly Critical For Chiplets And Photonics

 Warpage, heat, and brittleness can cause huge reliability problems for expensive designs.
May 21st, 2026 By Laura Peters

Mask Technology Faces A New Set Of Challenges

 Inspection limits, curvilinear adoption, data volumes, and high-NA EUV are converging t...
May 21st, 2026 By Gregory Haley

Options Grow For Standardizing Data Movement And Sharing Resources

 But figuring out which ones to use, and when to use them, isn't always clear.
May 20th, 2026 By Ed Sperling

Confusion Grows With More Interconnect Options And Tradeoffs

 Each standard serves a specific use case, so chip architects are choosing more than one...
May 18th, 2026 By Liz Allan

Chiplets Need A New Workflow

 Multi-die assemblies are facing full system-level challenges, but engineering teams nee...
May 14th, 2026 By Ann Mutschler

Gates Add Functionality, But Wires Create Problems

 Wires are treated as a lesser concern, but their neglect is becoming critical at advanc...
May 14th, 2026 By Brian Bailey

AI Accelerator Testing Depends On DFT Innovations

 Multi-die assemblies greatly increase the number of things that can go wrong, and the d...
May 12th, 2026 By Laura Peters

Smart Test Collides With The Data Chain

 Increasing complexity is limiting the ability of machine learning models to effectively...
May 12th, 2026 By Gregory Haley

more top stories »

Latest News

Chip Industry Week In Review

 Computex shows AI ecosystem; fully autonomous chip design; Intel targets AI racks; Nikon's 1.5 micron L/S litho; IC market rises; Apple's chiplet era; 4,500 chip...
June 5th, 2026 By The SE Staff

Blog Review: Jun. 3

 Verification IP; system-technology co-optimization; PCIe 7.0 ordering; design data challenges; process digital twins.
June 3rd, 2026 By Jesse Allen

Chip Industry Week In Review

 AI panel-level packaging innovations at ECTC; cool HBM; 2nm EDA tools; side-channel attacks in 2.5/3D; Huawei claims; IC talent initiative; glass core substrates;...
May 29th, 2026 By The SE Staff

more news »



Opinion

CPO Will Dominate Scale-Up: Link Budgets For dB And $ Are Key

 Optical interconnects are needed to boost GPU throughput and u...
June 10th, 2026 By Geoff Tate

Disturbance In Verification

 We have started to see what may be the largest disturbance in ...
June 8th, 2026 By Brian Bailey

more opinions »



Research

Chip Industry Technical Paper Roundup: June 8

 IGZO FeFET AI memories; zero-knowledge proof acceleration; Row...
By Linda Christensen

Research Bits: June 8

 Multi-tasking transistor; p-bit fabrication; tiny MoS2 nanotubes.
By Jesse Allen

Chip Industry Technical Paper Roundup: Jun. 2

 Fixed HW implementations of neural networks; LLM inference sca...
By Linda Christensen

more research »



Startup Corner

Startup Funding: Q1 2026

 Massive rounds for AI, EDA, and manufacturing; 80 startups rai...
By Jesse Allen

Startup Funding: Q4 2025

 More and bigger funding rounds for AI chips and AI for making ...
By Jesse Allen

more startups »

Videos

Building Multi-Agent Systems For ASIC Flows

June 10th, 2026

1 Megawatt Racks In Data Centers

June 3rd, 2026

The Evolution Of UCIe

June 2nd, 2026

Moving Defect Detection And Classification To The Edge

May 29th, 2026

Knowledge Centers / Entities, people and technologies explored

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