Special Reports

When The Test Cell Lies

By: Gregory Haley

As margins shrink and dies move into expensive packages, separating device failures from test-cell artifacts has become a first-order economic...
Rethinking Chip Verification

By: Ann Mutschler

Specification engineering is gaining traction as a potential solution to the verification bottleneck.
Creating A Moore’s Law For AI Scaling

By: Laura Peters

Scaling AI becomes the grand challenge of the Intelligence Era.

 more »

Top Stories

Startup Funding: Q2 2026

 Plenty of cash for AI and its enablers; 80 startups raise over $6B.
July 13th, 2026 By Jesse Allen

AI Is Rewriting The IP Playbook

 As the semiconductor ecosystem pivots to AI, it is transforming how IP is created, veri...
July 9th, 2026 By Ann Mutschler

Where Does Quantum Computing Stand?

 It's slowly emerging from research and heading toward high-volume production.
July 9th, 2026 By Bryon Moyer

An AI Model Fit For Purpose

 Using models outside the context in which they were created for can result in misleadin...
July 9th, 2026 By Brian Bailey

Multi-die Testing In The Field Must Build On Established Test Methodologies

 Having a device that works at time zero is no longer a guarantee of reliability over it...
July 7th, 2026 By Laura Peters

Inspection And Metrology Catching Up For High-Density Fan-Out Panel Packaging

 Optical methods need to comply with increasing warpage, finer RDL pitch, and trace size.
July 7th, 2026 By Anne Meixner

AI Data Centers And Auto Industry Converge On Same Issues

 The EV revolution relies on battery innovation, while AI data centers need a range of n...
July 2nd, 2026 By Liz Allan

Defending Against AI-Enabled Data Fusion

 As multimodal AI fuses data from billions of devices, attackers can weaponize detailed ...
July 2nd, 2026 By Ann Mutschler

Fine-Tuning Humanoid Vision And Movement

 Ongoing innovations are enabling humanoids to see and move more like humans; smell and ...
July 2nd, 2026 By Liz Allan

Observability Is A Missing Layer In AI-Era Chiplet Design

 In next-generation silicon, AI can interpret system behavior at scale, but only if obse...
July 1st, 2026 By Ann Mutschler

I/O Design Challenges Grow In AI Data Centers And HPC Clusters

 Physical I/Os can be a chokepoint for high-performance chips and high-speed interconnec...
June 25th, 2026 By Liz Allan

Verification Methodologies Struggle To Keep Up With AI

 Engineers are flooded with new capabilities. The problem now is how best to deploy them.
June 25th, 2026 By Brian Bailey

Executive Outlook: Agentic AI’s Impact On Chip Design

 Can engineers trust AI to get everything right in semiconductor design and verification?
June 25th, 2026 By Ed Sperling

Mask Economics Shape High-NA EUV Adoption

 Rising mask costs, tighter high-NA requirements, and new materials challenges are forci...
June 22nd, 2026 By Gregory Haley

How To Build Billions of Bumps

 Hybrid bonding permits unprecedented connection density.
June 18th, 2026 By Bryon Moyer

GaN Power Devices Go Vertical

 Why new designs and process flows could help overcome manufacturing challenges.
June 18th, 2026 By Katherine Derbyshire

Designing Chips That Can Explain Themselves

 On-die monitors, localized analytics, and lifecycle data are giving architects new ways...
June 17th, 2026 By Ann Mutschler

Wi-Fi Flies Higher As Edge AI Build-Out Takes Root

 Chip and system designers scramble to leverage existing and future standards as edge AI...
June 15th, 2026 By Ed Sperling

Agentic AI Is Changing Data Center Architectures

 Standalone GPUs are being replaced by heterogeneous SoCs and chiplets that combine CPUs...
June 11th, 2026 By Ann Mutschler

Can AI Create Missing Models?

 It depends on what those models are used, which also can have a big impact on the cost.
June 11th, 2026 By Brian Bailey

more top stories »

Latest News

EDA/SIP Revenue Up 12.7%; APAC Roars Back

 Market strength remains in double digits for most categories.
July 13th, 2026 By Ed Sperling

Chip Industry Week In Review

 Micron ups US investments; Apple's $30B deal; Solstice's buy; onsemi divests; diamonds for inspection; fault-tolerant quantum $; analog IMC; patent infringements;...
July 10th, 2026 By The SE Staff

Blog Review: July 8

 System complexity challenges; security Ethernet; IP for 3D-ICs; on-device gesture recognition; MRC protocol.
July 8th, 2026 By Jesse Allen

more news »



Opinion

Change Is Tough

 There has never been a time when change has become something e...
July 13th, 2026 By Brian Bailey

Data Center AI Growth Faces Challenging Bottlenecks

 Will AI growth grind to a halt due to bottlenecks?
July 6th, 2026 By Geoff Tate

more opinions »



Research

Research Bits: July 14

 Cerebellum-inspired memtransistor; fungal mycelium PCB; doping...
By Jesse Allen

Chip Industry Technical Paper Roundup: July 8

 Schottky barriers at Si/metal interfaces; agentic HLS; probab...
By Linda Christensen

Research Bits: July 6

 Neural net predicts semiconductor properties; ferroelectric ti...
By Jesse Allen

more research »



Startup Corner

Startup Funding: Q2 2026

 Plenty of cash for AI and its enablers; 80 startups raise over...
By Jesse Allen

Startup Funding: Q1 2026

 Massive rounds for AI, EDA, and manufacturing; 80 startups rai...
By Jesse Allen

more startups »

Videos

AI Models On The Edge

July 14th, 2026

How Far Left Can You Shift?

June 24th, 2026

New USB Standards: Benefits And Incompatibilities

June 23rd, 2026

Will Your Chip’s Memory Work As Expected?

June 22nd, 2026

Knowledge Centers / Entities, people and technologies explored

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy