Special Reports

When The Test Cell Lies

By: Gregory Haley

As margins shrink and dies move into expensive packages, separating device failures from test-cell artifacts has become a first-order economic...
Rethinking Chip Verification

By: Ann Mutschler

Specification engineering is gaining traction as a potential solution to the verification bottleneck.
Creating A Moore’s Law For AI Scaling

By: Laura Peters

Scaling AI becomes the grand challenge of the Intelligence Era.

 more »

Top Stories

Multi-die Testing In The Field Must Build On Established Test Methodologies

 Having a device that works at time zero is no longer a guarantee of reliability over it...
July 7th, 2026 By Laura Peters

Inspection And Metrology Catching Up For High-Density Fan-Out Panel Packaging

 Optical methods need to comply with increasing warpage, finer RDL pitch, and trace size.
July 7th, 2026 By Anne Meixner

AI Data Centers And Auto Industry Converge On Same Issues

 The EV revolution relies on battery innovation, while AI data centers need a range of n...
July 2nd, 2026 By Liz Allan

Defending Against AI-Enabled Data Fusion

 As multimodal AI fuses data from billions of devices, attackers can weaponize detailed ...
July 2nd, 2026 By Ann Mutschler

Fine-Tuning Humanoid Vision And Movement

 Ongoing innovations are enabling humanoids to see and move more like humans; smell and ...
July 2nd, 2026 By Liz Allan

Observability Is A Missing Layer In AI-Era Chiplet Design

 In next-generation silicon, AI can interpret system behavior at scale, but only if obse...
July 1st, 2026 By Ann Mutschler

I/O Design Challenges Grow In AI Data Centers And HPC Clusters

 Physical I/Os can be a chokepoint for high-performance chips and high-speed interconnec...
June 25th, 2026 By Liz Allan

Verification Methodologies Struggle To Keep Up With AI

 Engineers are flooded with new capabilities. The problem now is how best to deploy them.
June 25th, 2026 By Brian Bailey

Executive Outlook: Agentic AI’s Impact On Chip Design

 Can engineers trust AI to get everything right in semiconductor design and verification?
June 25th, 2026 By Ed Sperling

Mask Economics Shape High-NA EUV Adoption

 Rising mask costs, tighter high-NA requirements, and new materials challenges are forci...
June 22nd, 2026 By Gregory Haley

How To Build Billions of Bumps

 Hybrid bonding permits unprecedented connection density.
June 18th, 2026 By Bryon Moyer

GaN Power Devices Go Vertical

 Why new designs and process flows could help overcome manufacturing challenges.
June 18th, 2026 By Katherine Derbyshire

Designing Chips That Can Explain Themselves

 On-die monitors, localized analytics, and lifecycle data are giving architects new ways...
June 17th, 2026 By Ann Mutschler

Wi-Fi Flies Higher As Edge AI Build-Out Takes Root

 Chip and system designers scramble to leverage existing and future standards as edge AI...
June 15th, 2026 By Ed Sperling

Agentic AI Is Changing Data Center Architectures

 Standalone GPUs are being replaced by heterogeneous SoCs and chiplets that combine CPUs...
June 11th, 2026 By Ann Mutschler

Can AI Create Missing Models?

 It depends on what those models are used, which also can have a big impact on the cost.
June 11th, 2026 By Brian Bailey

PCIe Benefits From AI, Despite Scaling Protocols

 CXL is also gaining traction in AI processing, while MIPI and others are growing at the...
June 10th, 2026 By Bryon Moyer

AI Models Transform Defect Inspection And Review, But Can Fail To Scale

 Majority of AI initiatives falter; synthetic data gaining traction due to limited real-...
June 9th, 2026 By Laura Peters

Why Analog And Mixed-Signal Chips Resist Adaptive Test

 Analog behavior is difficult to compress into simple pass/fail decisions that could red...
June 9th, 2026 By Gregory Haley

Co-Packaged Optics Testing Faces Steep Data Center Ramp

 Scaling to tens of millions of CPO units per year requires the industry to first settle...
June 9th, 2026 By Anne Meixner

more top stories »

Latest News

Blog Review: July 8

 System complexity challenges; security Ethernet; IP for 3D-ICs; on-device gesture recognition; MRC protocol.
July 8th, 2026 By Jesse Allen

Chip Industry Week In Review

 S. Korea goes All In on AI; new Dresden power fab; Intel expansion; GM secures memory supply; AI power management funding; mature-node foundry capacity; 300mm fab...
July 3rd, 2026 By The SE Staff

Blog Review: July 1

 Ethernet auto-negotiation; multiphysics to avoid overdesign; PCB design reuse; mobile LLM quantization; modeling BSPDNs.
July 1st, 2026 By Jesse Allen

more news »



Opinion

Data Center AI Growth Faces Challenging Bottlenecks

 Will AI growth grind to a halt due to bottlenecks?
July 6th, 2026 By Geoff Tate

CPO Will Dominate Scale-Up: Link Budgets For dB And $ Are Key

 Optical interconnects are needed to boost GPU throughput and u...
June 10th, 2026 By Geoff Tate

more opinions »



Research

Chip Industry Technical Paper Roundup: July 8

 Schottky barriers at Si/metal interfaces; agentic HLS; probab...
By Linda Christensen

Research Bits: July 6

 Neural net predicts semiconductor properties; ferroelectric ti...
By Jesse Allen

Chip Industry Technical Paper Roundup: June 30

 Processing-using-DRAM interference; atomic-scale plasma proces...
By Linda Christensen

more research »



Startup Corner

Startup Funding: Q1 2026

 Massive rounds for AI, EDA, and manufacturing; 80 startups rai...
By Jesse Allen

Startup Funding: Q4 2025

 More and bigger funding rounds for AI chips and AI for making ...
By Jesse Allen

more startups »

Videos

How Far Left Can You Shift?

June 24th, 2026

New USB Standards: Benefits And Incompatibilities

June 23rd, 2026

Will Your Chip’s Memory Work As Expected?

June 22nd, 2026

Signoff Of Synthesis-Optimized Registers

June 17th, 2026

Knowledge Centers / Entities, people and technologies explored

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